Copper metallization has become widely adopted to form the multilevel interconnects required in today's ultra large scale integration (ULSI) semiconductor devices, due to its lower resistivity compared to aluminum and its improved electromigration resistance.
Multilevel interconnects consist in a network of copper lines (also called trenches) that are used to distribute various signals as well as power and ground to different areas of an integrated circuit. In order to be more real estate-efficient, these lines are stacked in several levels separated by a dielectric material and levels are connected to each other through vertical apertures called vias.
Lines and vias are formed using the damascene process sequence [See for example S. Wolf: “Silicon processing for the VLSI Era”, Vol. 4, p. 671-687] in which, at each level of the interconnect system, features are etched in the dielectric material and subsequently filled with copper before being planarized. A simplified version of this sequence can be described by:                dry etching of the dielectric material to form trenches and/or vias        deposition (conventionally by physical vapor deposition—PVD) of a Cu diffusion barrier (usually TaN/Ta) since copper is a fast diffuser and, during processing, could reach the underlying transistors built into silicon, causing device failures.        deposition of a “seed layer” of copper conventionally by PVD; this layer being required to overcome the high resistivity of the diffusion barrier layer onto which traditional copper electroplating processes produce non-contiguous three-dimensional clusters of Cu rather than a uniform film [See U.S. patent application 2005145499]        electrochemical deposition (electroplating) of copper to fill the vias and trenches.        planarization by chemical mechanical polishing (CMP) to leave copper lines inlaid in the dielectric. A robust formation technique for these lines and vias is required to ensure reliability of the ULSI devices.        
As device integration density increases, the width of lines, vias and other features on the circuits decreases, whereas the height or distance within and between the different levels remains fairly constant. As a result, the aspect ratio of the lines and vias, defined as their height-to-width ratio, tends to increase, making it difficult to fill them with copper.
These increasingly shrinking dimensions are a serious problem when physical deposition processes such as PVD have to be used as it is the case for the seed layer deposition in the damascene sequence. The copper seed layer, must be conformal and continuous even at very low thicknesses (around 10 nm) to ensure a proper gap filling by copper electroplating.
The PVD techniques are inherently directional and thus do not have adequate step coverage to meet these requirements for small features and/or for high aspect ratios. For example, a PVD process results in additional material to be deposited at the top corners of narrow features (overhang effect). This constriction of the feature width prior to copper electroplating makes achieving complete gapfill very challenging. Moreover, because of their dimensions, small features require ultra-thin seed layers (10 nm and below). This thickness requirement combined with the poor conformality of PVD processes result in discontinuities in the seed layer which appear on the feature sidewalls leading to defective and incomplete copper gap filling.
Alternate deposition techniques such as chemical vapor deposition (CVD) or atomic layer deposition (ALD) can be used to deposit a copper seed layer [see U.S. Pat. Nos. 6,887,522 and 6,849,122] but these processes still suffer from some type of overhang effect and they are prone to produce poor adhesion of copper to the underlying barrier layer due to the use of fluorine-containing precursors, thus compromising device yield.
These CVD and ALD processes cannot be used for filling features as their deposition rate is very low, making them incompatible with the high productivity environment of semiconductor device manufacturing.
Electroless copper deposition directly on the barrier material has been proposed to fill features. However, an extra activation step is often required and adhesion is also a problem. (See W. L. Goh and K. T. Tan “the use of electroless copper seed in electrochemical deposited copper interconnect”, Thin Solid Films, vol. 462-463, September 2004, p. 275-278).
For direct plating and filling, changing the diffusion barrier material to make it less resistive and more compatible with electroplating with traditional copper plating chemistries, has also been proposed [see U.S. Pat. No. 6,812,143]. This approach has the disadvantage of introducing a new material and requires significant rework of some of the processes of the damascene sequence.
As feature dimensions decrease, the use of seed layers will more significantly contribute to increase the effective aspect ratio and make gap filling by copper electroplating even more difficult, if merely possible.
An electrolytic copper bath capable of forming a seed layer of copper is normally not usable for gap filling since it generally leads to an inappropriate coating with the formation of a filling defect known as a “seam” (a central notch in the via, appearing when the filling gradient occurs predominantly from the lateral walls of the via). Such a seam may cause a structural weakness due to a locally low copper density. Furthermore, the seam may be a diffusion path for contaminants (said contaminants may for example be due to the use of chemical polishing solutions). Alternatively, traditional electroplating baths, such as those which are being used to fill up trenches after a copper seed step, cannot afford uniform coverage starting directly on the barrier material, due to ohmic drop effects: existing copper electroplating bath are indeed designed to perform bottom-up copper growth on a conductive surface. Last, filling trenches in a single step constitutes a difficult challenge as one is actually seeking the process to start as a conformal deposition, in order to avoid overhang and/or discontinuities, and then to continue in a non-conformal or bottom-up growth to secure complete seamless filling.
A gap fill capable single step electroplating performed directly on the diffusion barrier material would thus alleviate the above issues and constitute a solution not necessarily straightforward to the skilled person.
In addition, one should note that such a process would bring productivity gains as one single tool could be used to perform a sequence (seed deposition followed by trench/via filling) which today requires two equipments i.e. one for seed deposition and one for copper plating. This latter merit also suggests that the above-mentioned technical elements regarding the shrinking of dimensions are optional to motivate the introduction of the object of the present invention in manufacturing, and that this invention should be appealing from a cost standpoint alone.
Due to the limitations described above, there is a clear need for a process which can, in a single process step, using a single chemical bath: (1) directly plate copper onto the diffusion barrier regardless of its nature, and in particular onto the industry standard Ta based barriers, with good adhesion and (2) fill the features i.e. without using a copper seed layer and at a rate usable in manufacturing.